Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design

Physical design (PD) has always occupied a key position in the design flow because: 1) it defines the physical locations of transistors and interconnect wires; 2) it supports and handles different VLSI technologies for lithography and fabrication; and perhaps the most important; and 3) the scope of PD can span from early interactions with system planning, high-level synthesis, and logic synthesis, to back-end performance optimization, and design for manufacturing. Owing to its special position in the flow from RTL to layout, PD is considered to have high leverage in the optimization of chip area, power, thermal, and timing QoR, as well as the design turnaround time. In order to close the performance, power, and productivity gaps between microprocessors and ASICs, researchers have been focusing on different techniques to automate PD methods usually found in high-performance custom designs. Datapath synthesis, multibit flip-flop, nontree clock structures, and full-custom-quality clock buffer synthesis are examples of such efforts. Research efforts in automating those custom-designed PD methods may also help in the convergence of various design methodologies because designers tend to adopt distinct back-end flows for different design targets. In other words, the same PD flow can then be used for both high-performance microprocessors and low-power ASICs. Scaling has also become more and more difficult because of such different walls as thermal, power, ILP, memory, frequency , and lithography limits. Future design technologies and new manufacturing processes have recently been proposed, which is another major reason why newer PD topics involving, for instance, FinFETs, multiple patterning lithography process, electron-beam, 3-D designs, OPC/CMP co-optimization have been attracting more and more attention. As PD sits in between early planning, logic synthesis, and manufacturing process in the design flow, new PD algorithms are needed whenever next-generation technologies are introduced. In view of these trends, the papers in this Special Section highlight several studies on contemporary and emerging issues in physical design. The first paper demonstrates that today's CMOS-oriented EDA tools can be repurposed for the design of ASICs using the emerging vertical slit field effect transistors (VeSFETs). It shows that the VeSFET-based designs could have a power advantage over CMOS-based designs at the same performance. For the second paper, instead of replacing all registers with single-bit retention registers such that data can be retained during sleep mode, it replaces only selected registers with multibit retention registers to reduce the negative impacts on the area and leakage power that …